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functional block diagram 1 2 3 4 5 6 7 8 9 10 12 13 14 15 11 16 18-bit dac 18-bit serial register 18-bit serial register ad1868 ll dl ck dr lr dgnd nrl agnd nrr v l v b r v b l v s v o l v o r v s 18-bit dac + + v ref v ref rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a single supply dual 18-bit audio dac ad1868* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features dual serial input, voltage output dacs single +5 v supply 0.004% thd+n (typ) low power: 50 mw (typ) 108 db channel separation (min) operates at 8 3 oversampling 16-pin plastic dip or soic package applications portable compact disc players portable dat players and recorders automotive compact disc players automotive dat players multimedia workstations product description the ad1868 is a complete dual 18-bit dac offering excellent performance while requiring a single +5 v power supply. it is fabricated on analog devices abcmos wafer fabrication pro- cess. the monolithic chip includes cmos logic elements, bipo- lar and mos linear elements, and laser-trimmed thin-film resistor elements. careful design and layout techniques have re- sulted in low distortion, low noise, high channel separation, and low power dissipation. the dacs on the ad1868 chip employ a partially segmented architecture. the first three msbs of each dac are segmented into seven elements. the 15 lsbs are produced using standard r-2r techniques. the segments and r-2r resistors are laser trimmed to provide extremely low total harmonic distortion. the ad1868 requires no deglitcher or trimming circuitry. low noise is achieved through the use of two noise-reduction capacitors. each dac is equipped with a high performance output ampli- fier. these amplifiers achieve fast settling and high slew rate, producing 1 v signals at load currents up to 1 ma. the buffered output signal range is 1.5 v to 3.5 v. reference volt- ages of 2.5 v are provided, eliminating the need for false ground networks. a versatile digital interface allows the ad1868 to be directly connected to all digital filter chips. fast cmos logic elements allow for an input clock rate of up to 13.5 mhz. this allows for operation at 2 , 4 , 8 , or 16 the sampling frequency for each channel. the digital input pins of the ad1868 are ttl and +5 v cmos compatible. * protected by u.s. patent numbers: 3,961,326; 4,141,004; 4,349,811; 4,857,862; and patents pending. the ad1868 operates on +5 v power supplies. the digital sup- ply, v l , can be separated from the analog supply, v s , for re- duced digital feedthrough. separate analog and digital ground pins are also provided. in systems employing a single +5 volt power supply, v l and v s should be connected together. in bat- tery operated systems, operation will continue even with reduced supply voltage. typically, the ad1868 dissipates 50 mw. the ad1868 is packaged in either a 16-pin plastic dip or a 16- pin plastic soic package. operation is guaranteed over the tem- perature range of C35 c to +85 c and over the voltage supply range of 4.75 v to 5.25 v. product highlights 1. single-supply operation @ + 5 v. 2. 50 mw power dissipation (typical). 3. thd+n is 0.004% (typical). 4. signal-to-noise ratio is 97.5 db (typical). 5. 108 db channel separation (minimum). 6. compatible with all digital filter chips. 7. 16-pin dip and 16-pin soic packages. 8. no deglitcher required. 9. no external adjustments required.
rev. a C2C ad1868Cspecifications (typical at t a = +25 8 c and +5 v supplies unless otherwise noted) min typ max units resolution 18 bit digital inputs v ih 2.4 v v il 0.8 v i ih , v ih = v l 1.0 m a i il , v il = dgnd 1.0 m a maximum clock input frequency 13.5 mhz accuracy gain error 1 % of fsr gain matching 1 % of fsr midscale error 15 mv midscale error matching 10 mv gain linearity error 3db drift (0 c to +70 c) gain drift 100 ppm/ c midscale drift 100 m v/ c total harmonic distortion + noise 0 db, 990.5 hz AD1868N 0.004 0.008 % AD1868N-j 0.004 0.006 % C20 db, 990.5 hz AD1868N 0.020 0.08 % AD1868N-j 0.020 0.08 % C60 db, 990.5 hz AD1868N 2.0 5.0 % AD1868N-j 2.0 5.0 % channel separation 1 khz, 0 db 108 nil* db signal-to-noise ratio (with a-weight filter) 95 97.5 db d-range (with a-weight filter) 86 92 db output voltage output pins (v o l, v o r) output range ( 3%) 1v output impedance 0.1 w load current 1ma bias voltage pins (v b l, v b r) output voltage +2.5 v output impedance 350 w power supply specification, v l and v s 4.75 5 5.25 v operation, v l and v s 3.5 5.25 v +i, v l and v s = 5 v 10 14 ma power dissipation 50 70 mw temperature range specification 0 25 70 c operation C35 85 c storage C60 100 c *above 115 db. specifications subject to change without notice. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1868 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings* v l to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to 6 v v s to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to 6 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 v digital inputs to dgnd . . . . . . . . . . . . . . . . . . . . . C0.3 to v l soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300 c, 10 sec *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ad1868 rev. a C3C typical performance of the ad1868 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 0.5 2.5 4.5 6.5 8.5 10.5 12.5 14.5 frequency ?khz thd +n ?db ?0db ?0db 0db 16.5 18.5 20.5 figure 1. thd+n vs. frequency ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 4.4 4.6 4.8 5.0 5.2 5.4 voltage supply thd +n ?db ?0db ?0db 0db figure 3. thd+n vs. supply voltage ?0 ?0 ?00 140 thd +n ?db ?0 ?0 ?0 10 30 50 70 90 110 130 ?0 ?0 60db 20db 0db temperature ?? figure 5. thd+n vs. temperature 150 140 130 120 110 100 frequency ?hz channel separation ?db 10 3 10 4 figure 2. channel separation vs. frequency 8 6 4 2 0 ? ? ? 0 input amplitude ?db gain linearity error ?db ?00 ?0 ?0 ?0 ?0 ?0 0? 25? 70? figure 4. gain linearity error vs. input amplitude 90 80 70 60 50 40 supply modulation frequency ?hz psrr ?db 10 2 10 3 10 4 10 5 figure 6. power supply rejection ratio vs. frequency
ad1868 rev. a C4C pin configuration 1 2 3 4 5 6 7 8 9 10 12 13 14 15 11 16 ll dl ck dr lr dgnd nrl agnd nrr v l v b r ad1868 top view (not to scale) v s v s v o r v o l v b l definition of specifications total harmonic distortion + noise total harmonic distortion plus noise (thd+n) is defined as the ratio of the square root of the sum of the squares of the am- plitudes of the harmonics and noise to the amplitude of the fun- damental input frequency. it is usually expressed in percent (%) or decibels (db). d-range distortion d-range distortion is the ratio of the amplitude of the signal at an amplitude of C60 db to the amplitude of the distortion plus noise. in this case, an a-weight filter is used. the value speci- fied for d-range performance is the ratio measured plus 60 db. signal-to-noise ratio the signal-to-noise ratio is defined as the ratio of the amplitude of the output when a full-scale output is present to the ampli- tude of the output with no signal present. it is expressed in decibels (db) and measured using an a-weight filter. gain linearity gain linearity is a measure of the deviation of the actual output amplitude from the ideal output amplitude. it is determined by measuring the amplitude of the output signal as the amplitude of that output signal is digitally reduced to a lower level. a per- fect d/a converter exhibits no difference between the ideal and actual amplitudes. gain linearity is expressed in decibels (db). midscale error midscale error is the difference between the analog output and the bias when the twos complement input code representing midscale is loaded in the input register. midscale error is ex- pressed in mv. ordering guide thd + n package model @ f s snr option* AD1868N 0.008% 95 db n-16 ad1868r 0.008% 95 db r-16 AD1868N-j 0.006% 95 db n-16 ad1868r-j 0.006% 95 db r-16 *n = plastic dip; r = soic. pin designations 1 1v l digital supply (+5 volts) 1 2 ll left channel latch enable 1 3 dl left channel data input 1 4 ck clock input 1 5 dr right channel data input 1 6 lr right channel latch enable 1 7 dgnd digital common 1 8v b r right channel bias 1 9v s analog supply (+5 volts) 10 v o r right channel output 11 nrr right channel noise reduction 12 agnd analog common 13 nrl left channel noise reduction 14 v o l left channel output 15 v s analog supply (+5 volts) 16 v b l left channel bias functional description the ad1868 is a complete, voltage output dual 18-bit digital audio dac which operates with a single +5 volt supply. as shown in the block diagram, each channel contains a voltage reference, an 18-bit dac, an output amplifier, an 18-bit input latch, and an 18-bit serial-to-parallel input register. the voltage reference section provides a reference voltage and a false ground voltage for each channel. the low noise bandgap circuits produce reference voltages that are unaffected by changes in temperature, time, and power supply. the output amplifier uses both mos and bipolar devices and incorporates an npn class-a output stage. it is designed to pro- duce high slew rate, low noise, low distortion, and optimal fre- quency response. each 18-bit dac uses a combination of segmented decoder and r-2r architecture to achieve good integral and differential linearity. the resistors which form the ladder structure are fab- ricated with silicon-chromium thin film. laser trimming of these resistors further reduces linearity error, resulting in low output distortion. the input registers are fabricated with cmos logic gates. these gates allow fast switching speeds and low power con- sumption, contributing to the fast digital timing, low glitch, and low power dissipation of the ad1868.
ad1868 rev. a C5C 1 2 3 4 5 6 7 8 9 10 12 13 14 15 11 16 18-bit dac 18-bit serial register 18-bit serial register ad1868 ll dl ck dr lr dgnd nrl agnd nrr v l v b r v b l v s v o l v o r v s 18-bit dac + + v ref v ref functional block diagram analog circuit considerations grounding recommendations the ad1868 has two ground pins, designated as agnd (pin 12) and dgnd (pin 7). the analog ground, agnd, serves as the high quality reference ground for analog signals and as a return path for the supply current from the analog portion of the device. the system analog common should be located as close as possible to pin 12 to minimize any voltage drop which may develop between these two points, although the internal circuit is designed to minimize signal dependence of the analog return current. the digital ground, dgnd, returns ground current from the digital logic portion of the device. this pin should be connected to the digital common node in the system. as shown in figure 7, the analog and digital grounds should be joined at one point in the system. when these two grounds are remotely connected such as at the power supply ground, care should be taken to minimize the voltage difference between the dgnd and agnd pins in order to ensure the specified performance. power supplies and decoupling the ad1868 has three power supply input pins. v s (pins 9 and 15) provides the supply voltages which operate the analog por- tion of the device including the 18-bit dacs, the voltage refer- ences, and the output amplifiers. the v s supplies are designed to operate with a +5 v supply. these pins should be decoupled to analog common using a 0.1 m f capacitor. good engineering practice suggests that the bypass capacitors be placed as close as possible to the package pins. this minimizes the inherent induc- tive effects of printed circuit board traces. v l (pin 1) operates the digital portions of the chip including the input shift registers and the input latching circuitry. v l is also designed to operate with a +5 v supply. this pin should be by- passed to digital common using a 0.1 m f capacitor, again placed as close as po ssible to the package pin. figure 7 illustrates the cor- rect connection of the d igital and analog supply bypass capacitors. an important feature of the ad1868 audio dac is its ability to operate at reduced power supply voltages. this feature is very important in portable battery operated systems. as the batteries discharge, the supply voltage drops. unlike any other audio dac, the ad1868 can continue to function at supply voltages as low as 3.5 v. because of its unique design, the power require- ments of the ad1868 diminish as the battery voltage drops, fur- ther extending the operating time of the system. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 ll dl ck dr lr dgnd nrl agnd nrr v l v b r v b l v s v o l v o r ad1868 power supply 0.1? 0.1? 4.7? 4.7? v s figure 7. recommended circuit schematic noise reduction capacitors the ad1868 has two noise reduction pins designated as nrl (pin 13) and nrr (pin 11). it is recommended that external noise reduction capacitors be connected from these pins to agnd to reduce the output noise contributed by the voltage reference circuitry. as shown in figure 7, each of these pins should be bypassed to agnd with a 4.7 m f or larger capacitor. the connections between the capacitors, package pins and agnd should be as short as possible to achieve the lowest noise. using v b l and v b r the ad1868 has two bias voltage reference pins, designated as v b r (pin 8) and v b l (pin 16). these pins supply a dc reference voltage equal to the center of the output voltage swing. these bias voltages repl ace false ground networks previously required in single-supply audio syste ms. at the same time, they allow dc- coupled systems, improving audio performance. figure 8a illustrates the traditional approach used to generate false ground voltages in single-supply audio systems. this cir- cuit requires additional power and circuit board space. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16-bit latch 16-bit dac serial input register control logic ad1851 i out ? s dgnd nc clk le data +v l nc = no connect +v s trim msb adj i out agnd sj r f v out nc figure 8a. schematic using false ground
ad1868 rev. a C6C 1 2 3 4 5 6 7 8 9 11 12 13 14 16 15 ll dl ck dr lr dgnd nrl agnd nrr v l v s ad1868 + 5v v o l + 5v 10 v b l v o r v o l v o r v s v b r figure 8b. circuitry using voltage biases the ad1868 eliminates the need for false ground circuitry. v b r and v b l generate the required bias voltages previously generated by the false ground. as shown in figure 8b, v b r and v b l may be used as the reference point in each output channel. this permits a dc-coupled output signal path. this eliminates ac-coupling capacitors and improves low frequency performance. it should be noted that these bias outputs have relatively high output impedance and will not drive output currents larger than 100 m a without degrading the specified performance. distortion performance and testing the thd+n figure of an audio dac represents the amount of undesirable signal produced during reconstruction and playback of an audio waveform. therefore, the thd+n specification provides a direct method to classify and choose an audio dac for a desired level of performance. figure 1 illustrates the typical thd+n versus frequency perfor- mance of the ad1868. it is evident that the thd+n perfor- mance of the ad1868 remains stable at all three levels through a wide range of frequencies. a load impedance of at least 2 k w is recommended for best thd+n performance. analog devices tests and grades all ad1868s on the basis of thd+n performance. during the distortion test, a high speed digital pattern generator transmits digital data to each channel of the device under test. eighteen-bit data is latched into the dac at 352.8 khz (8 f s ). the test waveform is a 990.5 hz sine wave with 0 db, C20 db, and C60 db amplitudes. a 4096- point fft calculates total harmonic distortion + noise, signal-to-noise ratio, and d-range. no deglitchers or external adjustments are used. digital circuit considerations input data the ad1868 digital input port employs five signals: data left (dl), data right (dr), latch left (ll), latch right (lr) and clock (clk). dl and dr are the serial inputs for the left and right dacs, respectively. input data bits are clocked into the in- put register on the rising edge of clk. the falling edges of ll and lr cause the last 18 bits which were clocked into the serial registers to be shifted into the dacs, thereby updating the re- spective dac outputs. for systems using only a single latch sig- nal, ll and lr may be connected together. for systems using only one data signal, dr and dl may be connected together. data is transmitted to the ad1868 in a bit stream composed of 18-bit words with a serial, twos complement, msb first format. left and right channels share the clock (clk) signal. figure 9 illustrates the general signal requirements for data transfer for the ad1868. clk dl dr ll lr msb msb lsb lsb figure 9. control signals
ad1868 rev. a C7C timing figure 10 illustrates the specific timing requirements that must be met in order for the data transfer to be accomplished prop- erly. the input pins of the ad1868 are ttl and 5 v cmos compatible. the maximum clock rate of the ad1868 is specified to be at least 13.5 mhz. this clock rate allows data transfer rates of 2 , 4 , 8 , and 16 f s (where f s equals 44.1 khz). the applica- tions section of this data sheet contains additional guidelines for using the ad1868. lsb (18th bit) >15ns clk > 74./ ns >10ns >30ns >30ns data latch enable (le) >60ns >40ns >40ns >30ns bits clocked to shift register 2nd bit msb 1st bit next word >10ns internal dac input register updated with 18 most recent bits figure 10. input signal timing applications of the ad1868 the ad1868 is a high performance audio dac specifically de- signed for portable and automotive digital audio applications. these market segments have technical requirements fundamen- tally different than those found in the high-end or home-use market segments. portable equipment must rely on components which require low amounts of power to offer reasonable playing times. also, battery voltages drop as the end of the discharge cycle is approached. the ad1868s ability to operate from a single +5 v supply makes it a good choice for battery-operated gear. as the battery voltage drops, the power dissipation of the ad1868 drops. this extends the usable battery life. finally, as the battery supply voltage drops, the bias voltages and signal swings also drop, preventing signal clipping and abrupt degra- dation of distortion. figure 3 illustrates that thd+n perfor- mance of the ad1868 remains constant through a wide range of supply voltages. automotive equipment rely on components which are able to consistently perform in a wide range of temperatures. in addi- tion, due to the limited space available in automotive applica- tions, small size is essential. the ad1868 is able to satisfy both of these requirements. the device has guaranteed specified per- formance between 0 c and +70 c, and the 16-pin dip or 16- pin soic package is particularly attractive where overall size is important. since the ad1868 provides dc bias voltages, the entire signal chain can be dc-coupled. this eliminate ac-coupling capacitors from the signal path, improving low frequency performance and lowering system cost and size. in summary, the ad1868 is an excellent choice for battery op- erated portable or automotive digital audio systems. in the fol- lowing sections, some examples of high performance audio applications featuring the ad1868 are described. ad1868 with sony cxd2550p digital filter figure 11 illustrates an 18-bit cd player design incorporating an ad1868 dac, a sony cxd2550p digital filter and 2-pole antialias filters. this high performance, single supply design op- erates at 8 f s and is suitable for portable and automotive ap- plications. in this design, the cxd2550p filter transmits left and right channel digital data to the ad1868. the left and right latch signals, ll and lr, are both provided by the word clock signal (lrcko) of the digital filter. the digital data is converted to low distortion output voltages by the output amplifiers on the ad1868. also, no deglitching circuitry or exter nal adjustments are required. bypass capacitors, noise reduction capacitors and the antialias filter details are omitted for clarity. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 ll dl ck dr lr dgnd nrl agnd nrr v l v b r ad1868 1 2 3 4 5 6 7 8 11 12 13 14 15 16 18 17 test slot lrck0 cxd2550p 9 10 v dd bcko datar datal 1 2 3 4 5 6 8 7 agnd v s left channel output right channel output +5v power supply 8fs/4fs init v ss v s v o r v o l v b l v s figure 11. ad1868 with sony cxd2550p digital filter
ad1868 rev. a C8C additional applications in addition to cd player designs, the ad1868 is suitable for similar applications such as dat, portable musical instru- ments, laptop and notebook personal computers, and pc au- dio i/o boards. the circuit techniques illustrated are directly applicable in those applications. figures 12, 13, and 14 show connection diagrams for the ad1868 with popular digital filter chips from npc and yamaha. each application operates at 8 f s operation. please refer to the appropriate sections of this data sheet for additional information. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 ll dl ck dr lr dgnd nrl agnd nrr v b r v b l v o l v o r v s ad1868 1 2 3 4 5 6 7 8 21 22 23 24 25 26 28 27 bcko 9 20 v ss 1 dor dol wcko left channel output right channel output +5v power supply 10 19 11 18 12 17 13 16 14 15 v dd ow18 ow20 low pass filter low pass filter cob v l v ss 2 v s sm5813 figure 12. ad1868 with npc sm5813 digital filter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 ll dl ck dr lr dgnd nrl agnd nrr v l v b r v b l v s v o l v o r ad1868 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 bcko sm5818ap v ss dor dol wdco left channel output right channel output +5v power supply low pass filter low pass filter v dd v s figure 13. ad1868 with npc sm5818ap digital filter
ad1868 rev. a C9C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 ll dl ck dr lr dgnd nrl agnd nrr v l v s ad1868 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 ym3434 v ss dro dlo left channel output right channel output +5v power supply low pass filter low pass filter v dd 2 st bco wco 16/18 v b r v b l v dd 1 v s v o l v o r figure 14. ad1868 with yamaha ym3434 digital filter other digital audio components available from analog devices 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16-bit latch 16-bit dac serial input register control logic ad1856 dgnd nc clk le data nc = no connect trim msb adj agnd sj ? s +v l ? l +v s i out v out r f i out ad1856 16-bit audio dac complete, no external components required 16-pin dip or soic package standard pinout low cost 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18-bit latch 18-bit dac serial input register control logic ad1860 dgnd nc clk le data nc = no connect trim msb adj agnd sj ? s +v l ? l +v s i out v out r f i out ad1860 18-bit audio dac complete, no external components required 102 db snr minimum 16-pin dip or soic package standard pinout
ad1868 rev. a C10C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16-bit latch 16-bit dac serial input register control logic ad1851 i out ? s dgnd nc clk le data +v l nc = no connect +v s trim msb adj i out agnd sj r f v out nc ad1851 16-bit pcm audio dac 107 db snr minimum 16 f s capability 5 v supply reference ad1864 ? s agnd r f trim msb i out dgnd +v s 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 trim sj v out ? l dl ll msb i out agnd r f sj v out +v l dr lr ck reference 18-bit latch 18-bit dac 18-bit dac 18-bit latch + + ad1864 dual 18-bit audio dac complete, no external components high performance low crosstalk 24-pin dip thd+n = 0.004% (typical) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18-bit latch 18-bit dac serial input register control logic ad1861 dgnd nc clk le data nc = no connect trim msb adj agnd sj ? s +v l +v s i out v out r f i out nc ad1861 18-bit pcm audio dac 107 db snr minimum 16 f s capability 5 v supply reference ad1865 ? s agnd r f trim msb i out dgnd +v s 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 trim sj v out nc dl ll msb i out agnd r f sj v out +v l dr lr ck reference 18-bit latch 18-bit dac 18-bit dac 18-bit latch + + nc = no connect ad1865 dual 18-bit audio dac 107 db snr minimum 16 f s capability thd+n = 0.004% (typical) 5 v supply
ad1868 rev. a C11C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 voltage reference input & digital offset ad1862 ? s clk le data agnd r f trim nr 2 adj nr 1 i out dgnd 20-bit dac ? s +v l ? l +v s ad1862 20-bit, low noise audio dac 110 db snr minimum thd+n = 0.0019% (typical) 1 db gain linearity 16-pin plastic dip
ad1868 rev. a C12C outline dimensions dimensions shown in inches and (mm). c1478C7C10/90 printed in u.s.a. plastic dip (n) package 0.125 (3.18) min 0.035 (0.89) 0.18 (4.57) 0.3 (7.62) 0.87 (22.1) max 0.25 (6.35) 0.31 (7.87) 0.18 (4.57) max 0.011 (0.28) 18 9 16 0.018 (0.46) 0.033 (0.84) 0.1 (2.54) plastic soic (r) package 0.042 (1.07) 0.013 (0.32) 0.019 (0.49) 0.050 (1.27) ref 0.104 (2.65) 0.012 (0.3) 1 8 9 16 0.413 (10.50) 0.419 (10.65) 0.299 (7.60) 0.030 (0.75)

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